Last modified
January 6, 2004

  Seminar Abstract
Center for Data Intensive Computing


 
 


 

The QCDOC Supercomputer: Hardware, Software, and Performance

An overview is given of the QCDOC architecture, a massively parallel and highly scalable computer optimized for lattice QCD using system-on-a-chipm technology. The heart of a single node is the PowerPC-based QCDOC ASIC, developed in collaboration with IBM Research, with a peak speed of 1 GFlop/s. The nodes communicate via high-speed serial links in a 6-dimensional mesh with nearest-neighbor connections.
Highly optimized four-dimensional QCD code obtains over 50% efficiency, even for problems of fixed computational difficulty run on tens of thousands of nodes. We also provide an overview of the QCDOC operating system, which manages and runs QCDOC applications on partitions of variable dimensionality.



 
























Top of Page

   

 




Copyright © 1999 Brookhaven National Laboratory ALL RIGHTS RESERVED
Comments/Sugestions about this site contact: Webmaster