2/11/00

9:26 AM 2/11/00    old/ing_basic


Number of Macrocells is 102
Number of GLBs is 29
Number of product terms is 204
Maximum number of GLB levels is 5
Average number of inputs per GLB is 10.5
Average number of outputs per GLB is 3.5
Average number of product terms per GLB is 7.0
Routing: 1 tick.
Testing:
pcdp_init(0) - FAIL, wrong version and board type
sp pcdp_rwtest,7 - OK
sp ems_test,7 - should not work

9:52 AM 2/11/00    old/ing_sclr


Added 2 32bit scalers and 16 MUX8-1
Number of Macrocells is 174
Number of GLBs is 54
Number of product terms is 402
Maximum number of GLB levels is 4
Average number of inputs per GLB is 13.0
Average number of outputs per GLB is 3.2
Average number of product terms per GLB is 7.4
Routing 1\3 ticks
Testing:
pcdp_init(0) - FAIL, wrong version and board type
sp pcdp_rwtest,7 - OK, rare errors: ghosts in the upper byte of CSR0 (two types: 0x8036 instead of 0x36, 0x8452 instead of 0x52). There was only one clock delay for SREAD. Need to add one more trigger for SREAD genration.
sp ems_test,7 - should not work

10:03 AM 2/11/00    old/eng

Number of Macrocells is 265
Number of GLBs is 73
Number of product terms is 560
Maximum number of GLB levels is 5
Average number of inputs per GLB is 12.4
Average number of outputs per GLB is 3.6
Average number of product terms per GLB is 7.7
Routing: 8 ticks
Testing:
pcdp_init(0) -OK
sp pcdp_rwtest,7 - OK
sp ems_test,7
ems_test_nscalers = 1
ems_test_addr1Sc = 5
OK

20:06 2/11/00    EMS version 2/11

Problem with PCDP read/writing solved. The SWRITE had been delayed by 1 clock.
Number of Macrocells is 187
Number of GLBs is 75
Number of product terms is 376
Maximum number of GLB levels is 4
Average number of inputs per GLB is 8.7
Average number of outputs per GLB is 2.5
Average number of product terms per GLB is 5.0
Routing: 1 tick
pcdp_init(0) -OK
sp pcdp_rwtest,4 - OK
sp ems_test,4
ems_test_nscalers = 4
ems_test_addr1Sc = 4
OK on all boards.
sch and jed files were saved to ems/save

10:53 2/14/00    EMS version 2/11

Removed Preserve=Y on MSEL and CO

Number of Macrocells is 189
Number of GLBs is 79 (this is close to the limit)
Number of product terms is 380
Maximum number of GLB levels is 4
Average number of inputs per GLB is 8.8
Average number of outputs per GLB is 2.4
Average number of product terms per GLB is 4.8
Routing: 1 tick

Changed MAX_INPUTS from 10 to 16. Routing is OK.

In general, if a simple design does not route, one must decrease MAX_INPUTS.

Number of Macrocells is 182
Number of GLBs is 65 (Decreased)
Number of product terms is 406
Maximum number of GLB levels is 3 (I think this should give less delay)
Average number of inputs per GLB is 11.2
Average number of outputs per GLB is 2.8
Average number of product terms per GLB is 6.2
Routing: 1 tick.

2/14 13:52    EMM

Number of Macrocells is 190
Number of GLBs is 58
Number of product terms is 368
Maximum number of GLB levels is 3
Average number of inputs per GLB is 10.7
Average number of outputs per GLB is 3.3
Average number of product terms per GLB is 6.3
Routing: 1 tick.

2/15 9:00    TrgManL0

Number of Macrocells is 231
Number of GLBs is 76
Number of product terms is 490
Maximum number of GLB levels is 5
Average number of inputs per GLB is 10.7
Average number of outputs per GLB is 3.0
Average number of product terms per GLB is 6.4
Routing: 2 ticks.

TrgManL1

Post-Route Design Implementation
--------------------------------

Number of Macrocells:        223
Number of GLBs:            67
Number of IOCs:            109
Number of DIs:            0
Number of GLB Levels:        7

Added 8 8-bit scalers for all inputs. Routing unsuccessful.
After combining CSR0 and Pr03 and setting MAX_INPUT to 16 it was possible to route.

Number of Macrocells is 246
Number of GLBs is 74
Number of product terms is 514
Maximum number of GLB levels is 6
Average number of inputs per GLB is 10.2
Average number of outputs per GLB is 3.3
Average number of product terms per GLB is 6.9

2/16/00 9:23    TrgManL0

EN register moved to CSR0, Added TCosm.

Number of Macrocells is 226
Number of GLBs is 75
Number of product terms is 501
Maximum number of GLB levels is 5
Average number of inputs per GLB is 10.8
Average number of outputs per GLB is 3.0
Average number of product terms per GLB is 6.7

Note: The L0 signal is 5 ns faster than LoPulse. Don't know why.

2/16/00 21:39    The trigger system is working.

Design: trgmanl0
Number of Critical Pins: 16
Number of Free Pins: 0
Number of Locked Pins: 103
Nets with Fanout of 32: 1
Average Fanout per Net: 2.97
GLBs with 17 Input(s): 13
Average Inputs per GLB: 11.09
Average Outputs per GLB: 3.20
Number of GLB Registers: 165
Number of Macrocells:        237
Number of GLBs:            75
Number of IOCs:            101
Number of DIs:            0
Number of GLB Levels:        5

Design: trgmanl1
Number of Critical Pins: 2
Number of Free Pins: 0
Number of Locked Pins: 86
Nets with Fanout of 31: 1
Average Fanout per Net: 2.61
GLBs with 17 Input(s): 1
Average Inputs per GLB: 10.04
Average Outputs per GLB: 3.29
Number of GLB Registers: 192
Number of Macrocells:        257
Number of GLBs:            79
Number of IOCs:            84
Number of DIs:            0
Number of GLB Levels:        3

3/10/00 18:52    FASTBUS performance

Reading 2.7kB of FB data + 29 kB Infoblock.
The FB reading time (NIM1) is 1.7 msec
The sending time (NIM3) is 3.8 msec
The Ethernet performance is therefore 32kB/3.8msec = 8.4 MB/sec
The phatdaq shows 5.7 MB/RTsec, 24.4 MB/CPUsec

For short Infoblock
FB reading = 1.5 msec (1.8 MB/sec)
Sending = 0.37 msec. This gives 2.7/.37 = 7.3 MB/sec

Long Infoblock = 500 KB
FB reading 6.9 = msec (78 MB/sec)
Sending = 58.9 msec (8.56 MB/sec)

Long Infoblock = 500 KB, Handshake per event.
FB reading 6.9 = msec (78 MB/sec)
Sending = 58.9 msec (8.56 MB/sec)

Summary: Ethernet handshake does not increase the overhead.

To improve sending performance we can try to remove waiting for zbuf ready in send_event. (Then one need to copy the event to the intermediete buffer)