Board parameters:
Name | Description | ID | Type | ||
EMM | Event Manager Master | 6 | 0 | ||
EMS: | Event Manager Slave | 7 | 1 | ||
TML0 | Trig Manager L0 | 4 | 2 | ||
TML1 | Trig Manager L1 | 5 | 3 |
unld "phatdaqLib.o"
ld </export/home/phobos/phatdaq/roc/src/phatdaqLib.o
First, we need to initialize some software parameters:
pcdp_init(0)
You should see status of all available boards (maximum 8) in the crate.
To see that the register access is OK, change the setting of the SW2 and check the changes using pcdp_init(0)
Clear all scalers/registers executing Done (CSR1=0x8000) and Clear_Scalers (CSR1=0x4000) commands on board 7:
pcdp_set(7,1,0xC000)
Use pcdp_init(0) to see the
TML0, Level 0 Trigger Board. |
Board # |
4 |
|||||
Word |
Byte |
Signals |
Read |
Write |
|||
0 |
1 |
CSR[12:15] |
N/A |
same |
|||
0 |
1 |
EnbCI[8:11] |
Enable cosmic trigger inputs |
same |
|||
0 |
0 |
EnbCI[4:7] |
Enable beam trigger inputs |
same |
|||
0 |
0 |
EnbCI[0:3] |
Enable beam trigger inputs |
same |
|||
1 |
3 |
Switch |
On board switch ISW2 |
15-Reset all, 14-scalers, 13-L0 |
|||
1 |
3 |
Type |
Board Type |
N/A |
|||
1 |
2 |
Day |
Version |
N/A |
|||
1 |
2 |
Month |
Version |
N/A |
|||
2 |
5 |
CI[12:15] |
dECL Input port, 15-Veto, 14-CC |
CO[12:15] |
|||
2 |
5 |
CI[8:11] |
dECL Input port, TCosm[0:3] |
CO[8:11] |
|||
2 |
4 |
CI[4:7] |
dECL Input port, TBeam[4:7] |
TORV, HiPriO, TR0 |
|||
2 |
4 |
CI[0:3] |
dECL Input port, TBeam[0:3] |
L0,L0C,L0Pulse,TOR |
|||
3 |
7 |
TR[12:15] |
Latched CI |
||||
3 |
7 |
TR[8:11] |
Latched CI |
||||
3 |
6 |
TR[4:7] |
Latched CI |
||||
3 |
6 |
TR[0:3] |
Latched CI |
||||
4 |
9 |
ScL0 |
Scaler L0 |
||||
4 |
9 |
ScL0 |
Scaler L0 |
||||
4 |
8 |
ScL0 |
Scaler L0 |
||||
4 |
8 |
ScL0 |
Scaler L0 |
||||
5 |
11 |
ScL0 |
Scaler L0 |
||||
5 |
11 |
ScL0 |
Scaler L0 |
||||
5 |
10 |
ScL0 |
Scaler L0 |
||||
5 |
10 |
ScL0 |
Scaler L0 |
||||
6 |
13 |
ScTORV |
Vetoed triggers |
||||
6 |
13 |
ScTORV |
Vetoed triggers |
||||
6 |
12 |
ScTORV |
Vetoed triggers |
||||
6 |
12 |
ScTORV |
Vetoed triggers |
||||
7 |
15 |
ScTOR |
Applied triggers |
||||
7 |
15 |
ScTOR |
Applied triggers |
||||
7 |
14 |
ScTOR |
Applied triggers |
||||
7 |
14 |
ScTOR |
Applied triggers |
||||
8 |
17 |
ScT1 |
Scaler CI1 |
||||
8 |
17 |
ScT1 |
Scaler CI1 |
||||
8 |
16 |
ScT0 |
Scaler CI0 |
||||
8 |
16 |
ScT0 |
Scaler CI0 |
||||
9 |
19 |
ScT3 |
Scaler CI3 |
||||
9 |
19 |
ScT3 |
Scaler CI3 |
||||
9 |
18 |
ScT2 |
Scaler CI2 |
||||
9 |
18 |
ScT2 |
Scaler CI2 |
||||
10 |
21 |
ScTCosm |
Scaler Cosmic |
||||
10 |
21 |
ScTCosm |
Scaler Cosmic |
||||
10 |
20 |
ScT4 |
Scaler CI4 |
||||
10 |
20 |
ScT4 |
Scaler CI4 |
||||
11 |
23 |
N/A |
|||||
11 |
23 |
N/A |
|||||
11 |
22 |
N/A |
|||||
11 |
22 |
N/A |
|||||
TML1, Level 1 Trigger Board. |
Board # |
5 |
|||||
Word |
Byte |
TML1 |
Read |
Write |
|||
0 |
1 |
PR0 |
Prescaler 3 setting |
same |
|||
0 |
1 |
PR1 |
Prescaler 2 setting |
same |
|||
0 |
0 |
PR2 |
Prescaler 1 setting |
same |
|||
0 |
0 |
PR3 |
Prescaler 0 setting |
same |
|||
1 |
3 |
Switch |
On board switch ISW2 |
15-Reset, 14-Scaler reset, 13-L1 reset |
|||
1 |
3 |
Type |
Board Type |
N/A |
|||
1 |
2 |
Day |
Version |
N/A |
|||
1 |
2 |
Month |
Version |
N/A |
|||
2 |
5 |
CI[12:15] |
ExtL1R, ZDC, CC, Veto |
||||
2 |
5 |
CI[8:11] |
CI[8:11] |
||||
2 |
4 |
CI[4:7] |
Pr[4:7] |
||||
2 |
4 |
CI[0:3] |
L0, Pr[1:3] |
||||
3 |
7 |
0 |
Prescaler 7 setting |
||||
3 |
7 |
0 |
Prescaler 6 setting |
||||
3 |
6 |
PRQ[4:7] |
Latched prescaled triggers |
Prescaler 5 setting |
|||
3 |
6 |
PRQ[0:3] |
Latched prescaled triggers |
Prescaler 4 setting |
|||
4 |
9 |
ScCI1 |
ScCI1 |
||||
4 |
9 |
ScCI1 |
ScCI1 |
||||
4 |
8 |
ScCI0 |
ScCI0 |
||||
4 |
8 |
ScCI0 |
ScCI0 |
||||
5 |
11 |
ScCI3 |
ScCI3 |
||||
5 |
11 |
ScCI3 |
ScCI3 |
||||
5 |
10 |
ScCI2 |
ScCI2 |
||||
5 |
10 |
ScCI2 |
ScCI2 |
||||
6 |
13 |
ScCI5 |
ScCI5 |
||||
6 |
13 |
ScCI5 |
ScCI5 |
||||
6 |
12 |
ScCI4 |
ScCI4 |
||||
6 |
12 |
ScCI4 |
ScCI4 |
||||
7 |
15 |
ScL1 |
Scaler of L1 |
||||
7 |
15 |
ScL1 |
Scaler of L1 |
||||
7 |
14 |
ScFC |
Scaler of Fast Clear pulses |
||||
7 |
14 |
ScFC |
Scaler of Fast Clear pulses |
||||
EMM, Event Manager Master Board. |
Board # |
6 |
|||||
Word |
Byte |
EMM |
Read |
Write |
|||
0 |
1 |
Enable,Trig |
15-Trigger |
12-Enable, 13:14-Disable T1:T2 |
|||
0 |
1 |
IL[0:2],IE |
contents |
8:10-Interrupt level, 11-Int enable |
|||
0 |
0 |
IV[4:7] |
contents |
Interrupt vector |
|||
0 |
0 |
IV[0:3] |
contents |
Interrupt vector |
|||
1 |
3 |
Switch |
On board switch ISW2 |
||||
1 |
3 |
Type |
Board Type |
||||
1 |
2 |
Day |
Version |
||||
1 |
2 |
Month |
Version |
||||
2 |
5 |
CI[12:15] |
CI[11:15] |
14-EvStrobe, 15-TrigPulse |
|||
2 |
5 |
CI[8:11] |
8-Trig2, 9-Veto01, 10-Ack2 |
Pulsed CO[8:11] |
|||
2 |
4 |
CI[4:7] |
4-Trig1, 5-Veto02, 6-Ack1 |
CO[4:7] |
|||
2 |
4 |
CI[0:3] |
0-Trig0 |
0-Busy, CO[1:3] |
|||
3 |
7 |
DP[12:15] |
Event type/command |
||||
3 |
7 |
DP[8:11] |
Event type/command |
||||
3 |
6 |
DP[4:7] |
Event number |
||||
3 |
6 |
DP[0:3] |
Event number |
||||
4 |
9 |
ScTrg[28:31] |
Accepted triggers |
||||
4 |
9 |
ScTrg[24:27] |
Accepted triggers |
||||
4 |
8 |
ScTrg[20:23] |
Accepted triggers |
||||
4 |
8 |
ScTrg[16:19] |
Accepted triggers |
||||
5 |
11 |
ScTrg[12:15] |
Accepted triggers |
||||
5 |
11 |
ScTrg[8:11] |
Accepted triggers |
||||
5 |
10 |
ScTrg[4:7] |
Accepted triggers |
||||
5 |
10 |
ScTrg[0:3] |
Accepted triggers |
||||
6 |
13 |
ScTVeto |
Vetoed triggers |
||||
6 |
13 |
ScTVeto |
Vetoed triggers |
||||
6 |
12 |
ScTapp |
Applied triggers |
||||
6 |
12 |
ScTapp |
Applied triggers |
||||
7 |
15 |
0 |
|||||
7 |
15 |
0 |
|||||
7 |
14 |
CIr |
Latched inputs |
||||
7 |
14 |
CIr |
Latched inputs |
||||
EMS, Event Manager Slave Board. |
Board # |
7 |
|||||
Word |
Byte |
EMS |
|||||
0 |
1 |
Enable,Trig |
15-Trigger |
12-Enable, 13:14-Split0:1 |
|||
0 |
1 |
IL[0:2],IE |
contents |
8:10 Interrupt level, 11 Int enable |
|||
0 |
0 |
IV |
contents |
Interrupt vector |
|||
0 |
0 |
IV |
contents |
Interrupt vector |
|||
1 |
3 |
Switch |
On board switch ISW2 |
15-Done, 14-Reset saclers, 13-icrement |
|||
1 |
3 |
Type |
Board Type |
||||
1 |
2 |
Day |
Version |
||||
1 |
2 |
Month |
Version |
||||
2 |
5 |
CI/CO12:15] |
15-Handshake |
13-MyTrig, 14-Veto, 15-Ack |
|||
2 |
5 |
CI/CO[8:11] |
CI[8:11] |
CO[8:11] |
|||
2 |
4 |
CI/CO[4:7] |
CI[4:7] |
CO[4:7] |
|||
2 |
4 |
CI/CO[0:3] |
CI[0:3] |
CO[0:3] |
|||
3 |
7 |
DP[12:15] |
Event type/command |
||||
3 |
7 |
DP[8:11] |
Event type/command |
||||
3 |
6 |
DP[4:7] |
Event number |
||||
3 |
6 |
DP[0:3] |
Event number |
||||
4 |
9 |
Sc0 |
Scaler CI0 |
||||
4 |
9 |
Sc0 |
Scaler CI0 |
||||
4 |
8 |
Sc0 |
Scaler CI0 |
||||
4 |
8 |
Sc0 |
Scaler CI0 |
||||
5 |
11 |
Sc2 |
Scaler CI0/2 |
||||
5 |
11 |
Sc2 |
Scaler CI0/2 |
||||
5 |
10 |
Sc2 |
Scaler CI0/2 |
||||
5 |
10 |
Sc2 |
Scaler CI0/2 |
||||
6 |
13 |
Sc1 |
Scaler CI1 |
||||
6 |
13 |
Sc1 |
Scaler CI1 |
||||
6 |
12 |
Sc1 |
Scaler CI1 |
||||
6 |
12 |
Sc1 |
Scaler CI1 |
||||
7 |
15 |
Sc3 |
Scaler CI1/3 |
||||
7 |
15 |
Sc3 |
Scaler CI1/3 |
||||
7 |
14 |
Sc3 |
Scaler CI1/3 |
||||
7 |
14 |
Sc3 |
Scaler CI1/3 |
The board ID identifies the board in the A24 VME address space.
The ID is set on the board switch SW3, positions A08, A09, A10.
The local address is usually 0xfa000000 + ID*0x100
Defined inside the chip, read: CSR1.9:10