Proposal 2. Shifted clock register
Program
part of the STLM as a n-bit register. Connect T0A to D inputs of the register, connect T0B to the clock inputs using delay line
(twisted pair cable with 3 cm spaced connectors). Requires n bits to cover 2*n*3 cm vertex range.
Output of the register will reflect time difference. For example 000111 means that T0B is three taps
prior the front of T0A, 111000 means
that T0B is three taps prior the
end of T0A.
Pros:
•Very easy to implement
•Can be modeled now using PCDP board
•
Cons:
•May not work. As pointed by Wojtek Skulski the main problem is
flip-flop metastability (see http://www.onsemi.com/pub/Collateral/AN1504-D.PDF).
•Too delicate to adjust
•Very sensitive to the noise on the board
•Occupies n+1 inputs of the STLM
•Requires calibration