Thursday, June 25, 2026, 12:00 pm — Videoconference / Virtual Event (see link below)
Erasure qubits—-qubits designed to have an error profile that is dominated by detectable leakage errors—-are a promising way to cut down the resources needed for quantum error correction. There have been several recent experiments demonstrating erasure qubits in superconducting quantum processors, most notably the dual-rail qubit defined by the one-photon subspace of two coupled cavities. An outstanding challenge is that the ancillary transmons needed to facilitate erasure checks and two-qubit gates introduce a substantial amount of noise, limiting the benefits of working with erasure-biased qubits. I will show how to suppress the adverse effects of transmon-induced noise while performing erasure checks or two-qubit gates. I will present control schemes for these operations that suppress erasure check errors by two orders of magnitude and reduce the logical two-qubit gate infidelities by up to three orders of magnitude. Starts at 12:00 p.m. ET/9:00 a.m. PT.
Hosted by: Kai-Mei Fu - C2QA Deputy Director, University of Washington
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