MAR/09/2001
By Miro PLESKO, MIT_LNS.EF
When FEC_CU system is powered up, it starts
downloading data bit stream from U513 (XC17256E) CU serial PROM into U514
(XC4013E_PQ240C) XILINX device.
End of this data downloading is indicated by LED501.
When data downloading is done the light of this LED will be turned on.
After data downloading, XILINX start
setup default values for thirty-two bias voltage levels on the FEC_CU signal
board (eight bias voltages per one port) by four devices ( MAX 529CAG )
residing in board position U103, U203, U303, U403.
Default voltage level values are selectable by user
( there must by programmed new PROM XC17256E for U512 device location with new
voltage level options ).
Information about these thirty-two bias voltage
levels, XILINX reads from serial PROM U512 (XC17256E) from the first four rows
( see table T1 ). For changing voltage levels are allowed change ONLY bold
numbers in the firs four rows. Other numbers in these rows, are pointers into
hardware device outputs.
Voltage levels are possible set from minus two up to
plus two volts by “FEC INVERSE CODE” coded hexadecimal value of these voltage
levels.
Calculation voltage levels in “FEC INVERS CODE” we
do by this sequence:
. First we must convert desired voltage level into
HEX number by equation ( 1 )
HEX[ in counts ] = HEX( INT( 64( V[ in volts ] +
2 ) ) ); ( 1 )
. Add leading zero ( if necessary ) to get two digit
place result.
. Convert this number into binary code.
. This binary number rewrite in opposite order (
i.e. zero bit is as seventh bit, first bit is as sixth bit, etc. )
. Convert this binary number back into hexadecimal
number and use it as your desired voltage level.
Example: Convert
minus 340mV into “FEC INVERSE CODE”.
HEX[ in counts ] = HEX(
INT( 64( - 0.34 + 2
) ) ) = HEX( 106 ) = 6A;
6A è 0110 1010 è 0101 0110 è 56;
So we have result: minus
340mV is in “FEC INVERSE CODE” is 56 units.
The fifth row, is the command for hardware MAX
529CAG devices in the location U103, U203, U303 and U403, which select full
buffered output modes and NOP command after that.
Table T1:
80 69 80 69 80 69 80 69 40 3E 40 3E 40 3E 40 3E
20 56 20 56 20 56 20 56 10 B5 10 B5 10 B5 10 B5
08 B3 08 B3 08 B3 08 B3 04 02 04 02 04 02 04 02
02 01 02 01 02 01 02 01 01 01 01 01 01 01 01 01
00 FF 00 FF 00 FF
00 FF 00 00 00 00 00 00 00 00
67 45 23 01 55 55 DE 80 FF FF FF FF FF FF FF FF
When all bias voltages are set, the command for turn on plus and minus two volts is issued, and then after this is issued command for turning on high voltage.
Next action is initialization of all
internal registers and state machines in the XILINX control system. There are
running these actions:
. Start running loading
action of buffers, which hold values for string length configurations and FEC
number.
Strings length information is also in the PROM U512 ( XC17256E )
in the last ( i.e. sixth ) row in
table T1 as a first four bold numbers ( see table T1 ).
Information about each string length is as a multiple of
sixty-four modulo, placed into one digit location. Location where is bold
number zero is dedicated for string number zero, location where is bold number
one is dedicated for string number one, etc. up till bold number seven.
Each information is written
in “FEC INVERSE CODE”.
Example:
. Reading control data from control bus via J502
forty pins connector and data receivers.
. Programming G-link transmitter U501 ( HDMP-1022 ),
FIFO devices ( CY7C457 )
for requested action and digital data multiplexers for requested data flow
directions.
. Resetting XILINX internal counters and VA chips.
. Establishing proper control signal sequences for
VA chips, analog to digital converters, digital multiplexers, FIFOs and G-link
transmitter. Start monitoring thirty-two analog entities and waiting for any
command configuration from DMU via control bus (connected into J502 connector)
on which will respond by particular action.
FEC_CU run in four modes (mode_0 = set mode, mode_1 = test mode, mode_2 = calibration mode, mode_3 = run mode) and is monitoring thirty-two analog data entities.
FEC_CU read data from VA chips with frequency 2.5MHz via eight strings (each with maximum length 768 channels) over four ports (each port has two strings).
FEC_CU is formatting all data into proper data protocol and then serially transmitted via G-link with speed 25Mbytes/sec.
MODE_X (mode1, mode0)
Command MODE_X (mode1, mode0) is
coming from DMU via data bus connected into J502 connector. By this command is
possible select one from four modes (MODE_0, MODE_1, MODE_2 or MODE_3).
In this mode is possible issued command BOOT, RESET
and is possible modified any bias voltage output from thirty-two bias voltages
by three signals CS_DAC, CLK_DAC and DIN_DAC which are issued during this mode
MODE_0.
BOOT command should be USED ONLY if HIGH VOLTAGE is
OFF, because by this command XILINX switch off all output going signals from
XILINX and all XILINX pins are set into tree-state condition. This may affect
some silicon functionality.
Purpose of this command is following, if by error
detection is found that FEC_CU is not properly operating we can reboot XILING.
By this action XILINX environment will be refreshed and all bias voltages will
be set into default values. All registers, buffers, G-link, VA chips and FIFOs
will be reset.
RESET command (i.e. negative pulse respect DMU) is
possible issued any time in this zero mode. This command in other modes is not
effective (there is inhibited). This command will reset all VA chips.
In this mode, data acquisition path
is set by multiplexing devices (IDT 74FST163214PA) U122, U123, U222, U223,
U322, U323, U422 and U423 so, that data as check board pattern are supplied
into FIFO inputs (instead of converted data from analog to digital converters
from VA chips).
Otherwise the system in this mode (MODE_1) work and
behave exactly same as in mode three (MODE_3). See below MODE_3 for father
information.
In this mode calibration state machine CAL_STM is waiting for positive (respect CAL_STM) signal L2. If state machine CAL_STM do not receive this L2 signal, system in this mode is not sensitive for other signals.
If positive signal L2 came then CAL_STM will issue signal SIFT_IN and one clock pulse CLK for VA chips (output bus driver will created one pare of complementary signals CLK_B and CLK).
After this action CAL_STM is waiting for negative (respect CAL_STM) signal L1. Before this L1 signal, DMU should issue calibration signal SYNC_CAL, which will release from calibration modules, calibration pulse for VA chips.
Voltage level for this calibration pulse is possible set from DMU by proper sequences of signals CS_DAC, CLK_DAC and DIN_DAC, which are issued during this MODE_2 mode.
Then after issuing of SYNC_CAL, and after proper peaking time, should by issued negative (respect CAL_STM) signal L1.
For this negative L1 signal CAL_STM is waiting. If L1 will came, CAL_STM create HOLD signal, wait for proper number of CONVCLK pulses (which take care for data latency in CYPRESS DAC) and will issued WE signal.
This WE signal enable write converted data information into FIFO devices on proper clock edge.
Then CAL_STM take off HOLD signal, issue next CLK for VA chips and wait for next negative L1 signal.
There must be minimum seven hundred seventy sequences with L1 and SYNC_CAL signals in any string configuration.
Setting of negative level L2_BUSY will indicate proper quantity of these sequences and transmission action for G_LINK start proceeds.
After finish of transmission actions, signal L2_BUSY is removed and system is initialized for next calibration sequence.
MODE_3 (mode1 = 1, mode0 = 1), RUN MODE
In this mode STG_READ (string read) module is waiting for finishing of transmission (if there was any transmission process in progress). End of transmission is indicated by low level of XMT_BUSY (this signal GLK_XMIT unit creates).
If there is not any more transmission activities, then STG_READ module is wailing for negative (respect DMU) signal L1. This L1 signal create by falling edge the HOLD signal.
Next action is control by STRGX_RD (string read) state machine. This state machine is waiting for not glitch L1 signal, and then after receiving this not glitch L1 signal is father waiting for positive (respect DMU) signal L2.
If this L2 signal DOES NOT COME during TEN microseconds, system is initialized and waiting for new L1 and L2 signals pare.
By receiving L2 signal, signal L2_BUSY will be issued and STRGX_RD module start transmit proper signal sequences for reading of VA chips and data are read with frequency 2.5Mhz from VA chips.
This state machine also controls digitalization of analog signals with respecting ADC data latency and writes them into FIFOS.
There are read SEVEN HUNDRED SIXTY EIGHT channels from each string and there are eight strings.
This reading process from VA chips is realized parallel and so do not affect speed of reading because there is some string any way which have seven hundred sixty eight channels and by this string is define closing time for data reading.
After finishing of reading and if there is not MDB_BUSY signal, signal EVENT will be set by STRGX_RD state machine. This internal signal EVENT starts transmitting process.
TRANSMITING PROCESS
Internal signal EVENT issued by STRG_RD state machine is sensing by GLK_XMIT state machine.
Immediately as GLK_XMIT unit sensed EVENT signal from STRG_RD unit, start issuing command control sequences for data reading from all FIFO units, monitoring registers, data base registers, error status registers and start these data formatting into prescribed format which is read from configuration PROM (U512).
This GLK_XMIT unit in the same time control G_LINK serial transmitter, generate for this unit proper signals sequences and supply G_LINK transmitter inputs with proper data in proper time.
End action of transmission terminated signal L2_BUSY and prepares internal status registers for next transmission.
ERROR STATUS DESCRIPTION
First byte of the 17th word of “HEADER DATA FORMAT” (i.e. 34th byte of this block) carry information about “FIFO UNLOAD ERROR”.
This information represent error status of FIFO, which had not empty flag before loading of new data from the string ADC into FIFO.
If this error appear in the certain string FIFO, then corresponding bit to this FIFO location is set into logic one (e.g. for string#3 corresponding “FIFO UNLOAD ERROR” is bit#3, etc.). There are eight strings labeled from zero to seven.
In four bits of second byte of the 17th word of “HEADER DATA FORMAT” (i.e. 35th byte of this block) are these information:
. bit#0 is set into one if during busy signal B1 is new L1 trigger issued.
. bit#1 is set into one if L2 trigger is issued and there was not HOLD signal.
. bit#2 is set into one if during busy signal B2 there was new L2 issued.
. bit#3 is set into one if system load error appear (i.e. XILINX is not boot or bias voltages was not properly set).
First byte of the 18th word of “HEADER DATA FORMAT” (i.e. 37th byte of this block) is information about “SHIFT OUT ERROR” for each string output.
If in some string is not shift out, then in this corresponding bit to this string position is set into one.
There are eight strings with labeling from zero to seven, so here we have also eight bits of data error information.
DATA END IDENTIFICATOR
This information reside in the 19th word of “HEADER DATA FORMAT” what is the last word of header (38th and 39th bytes).
This “DATA END IDENTIFICATOR” is set into value AAAA (in hexadecimal representation).
This data value also assure that “FLAG BIT” for this word location (19th respect to data header origin) is always set into value one.
By this “FLAG BIT” and AAAA (in hexadecimal representation) value is possible estimated and separated one data entity from another one.
This value for “DATA END IDENTIFICATOR” is possible reprogrammed in PROM U512 (see above information).