NOV/19/99, By Miro Plesko
POWER IS TURNED ON.
When FEC_CU system is powered up, it starts downloading data bit stream from U513 (XC17256E) CU serial PROM into U514 (XC4013E_PQ240C) XILINX device. End of this data downloading is indicated by LED501. When data downloading is done the light of this LED will be turned on.
After data downloading XILINX start setting up default values for thirty-two bias voltage levels on the FEC_CU signal board (eight bias voltages per one port). Information about these default values XILINX reads from serial PROM U512 (XC17256E). When all bias voltages are set the command for turn on plus and minus two volts is issued, and then after this command there is issued command for high voltage turning on.
Next action is initialization of all internal registers and state machines in the XILINX control system. There start running action of setting up buffers for string length configurations and FEC number. Reading control data from control bus via J502 forty pins connector and data receivers. Programming G-link transmitter U501 (HDMP-1022), FIFO devices (CY7C457) for requested action and digital data multiplexers for requested data flow directions. Resetting XILINX internal counters and VA chips. Establishing proper control signal sequences for VA chips, analog to digital converters, digital multiplexers, FIFOs and G-link transmitter. Start monitoring thirty-two analog entities and waiting for any command configuration from DMU via control bus (connected into J502 connector) on which will respond by particular action.
FEC_CU run in four modes (mode_0 = set mode, mode_1 = test mode, mode_2 = calibration mode, mode_3 = run mode) and monitoring thirty-two analog data entities. Read data from VA chips with frequency 2.5MHz via eight strings (each with maximum length 768 channels) over four ports (each port has two strings). FEC_CU is formatting all data into proper data protocol and then serially transmitted via G-link with speed 25Mbytes/sec.
MODE_X (mode1, mode0)
Command MODE_X (mode1, mode0) is coming from DMU via data bus connected into J502 connector. By this command is possible select one from four modes (MODE_0, MODE_1, MODE_2, MODE_3).
MODE_0 (mode1 = 0, mode0 = 0), SET MODE.
In this mode is possible issued command BOOT, RESET and is possible modified any bias voltage output from thirty-two bias voltages by three signals CS_DAC, CLK_DAC and DIN_DAC which are issued during this mode MODE_0. BOOT command should be used ONLY if high voltage is off, because by this command XILINX switch off all output going signals from XILINX and all XILINX pins are set into tree-state condition. This may affect some silicon functionality. Purpose of this command is following, if by error detection is found that FEC_CU is not properly operating we can reboot XILING. By this action XILINX environment will be refreshed and all bias voltages will be set into default values. All registers, buffers, G-link, VA chips and FIFOs will be reset. RESET command (i.e. negative pulse respect DMU) is possible issued any time in this zero mode. This command in other modes is not effective (there is inhibited). This command will reset all VA chips.
MODE_1 (mode1 = 0, mode1 = 1), TEST MODE. Here, data acquisition path is set by multiplexing devices (IDT 74FST163214PA) U122, U123, U222, U223, U322, U323, U422 and U423 so that data as check board pattern are supplied into FIFO inputs (instead of converted data from analog to digital converters from VA chips). Otherwise the system in this mode (MODE_1) work and behave exactly same as in mode three (MODE_3). See below MODE_3 for father information.
MODE_2 (mode1 = 1, mode0 = 0), CALIBRATION MODE.
In this mode calibration state machine CAL_STM is waiting for positive (respect CAL_STM) signal L2. If state machine CAL_STM do not receive this L2 signal, system in this mode is not sensitive for other signals. If positive signal L2 came then CAL_STM will issue signal SIFT_IN and one clock pulse CLK for VA chips (output bus driver will created one pare of complementary signals CLK_B and CLK). After this action CAL_STM is waiting for negative (respect CAL_STM) signal L1. Before this L1 signal, DMU should issue calibration signal SYNC_CAL, which will release from calibration modules, calibration pulse for VA chips. Voltage level for this calibration pulse is possible set from DMU by proper sequences of signals CS_DAC, CLK_DAC and DIN_DAC, which are issued during this mode MODE_2. Then after issuing of SYNC_CAL, there after proper peaking time should by issued negative (respect CAL_STM) signal L1. For this negative L1 signal CAL_STM is waiting. If L1 will came, CAL_STM create HOLD signal, wait for proper number of CONVCLK pulses (which take care for data latency in CYPRESS DAC) and will issued WE signal which enable write this converted data information into FIFO devices on proper clock edge. Then CAL_STM take off HOLD signal, issue next CLK for VA chips and wait for next negative L1 signal. There must be minimum seven hundred seventy sequences with L1 and SYNC_CAL signals in any string configuration. Setting of negative level L2_BUSY will indicate proper quantity of these sequences and transmission action for G_LINK will proceed. After finishing of transmission actions, signal L2_BUSY will be removed and system is initialized for next calibration sequence.
MODE_3 (mode1 = 1, mode0 = 1), RUN MODE.
In this mode STG_READ (string read) module is waiting for finishing of transmission (if this transmission process is in progress). End of transmission is indicated by low level of XMT_BUSY (this signal GLK_XMIT unit creates). If there is not any more transmission activities then STG_READ module is wailing for negative (respect DMU) signal L1. This L1 signal is create by falling edge of the HOLD signal. Next action is control by STRGX_RD (string read) state machine. This state machine is waiting for not glitch L1 signal, and then after receiving this not glitch L1 signal is father waiting for positive (respect DMU) signal L2. If this L2 signal does not come during ten microseconds, system is initialized and waiting for new L1 and L2 signals. By receiving L2 signal, signal L2_BUSY will be issued and STRGX_RD module start transmit proper signal sequences for reading of VA chips and data are read with frequency 2.5Mhz from VA chips. This state machine also controls digitalization of analog signals with respecting ADC data latency and writes them into FIFOS. There are read seven hundred sixty eight channels from each string. There are eight strings. This reading process from VA chips is realized parallel and so do not affect speed of reading because there is some string any way which have seven hundred sixty eight channels and by this string is define closing time for data reading. After finishing of reading and if there is not MDB_BUSY signal, signal EVENT will be set by STRGX_RD state machine. This internal signal EVENT starts transmitting process.
TRANSMITING PROCESS.
Internal signal EVENT issued by STRG_RD state machine is sensing by GLK_XMIT state machine. Immediately as GLK_XMIT unit sensed EVENT signal from STRG_RD unit, start issuing command control sequences for data reading from all FIFO units, monitoring registers, data base registers, error status registers and start these data formatting into prescribed format which is read from configuration PROM (U512). This GLK_XMIT unit in the same time control G_LINK serial transmitter, generate for this unit proper signals sequences and supply G_LINK transmitter inputs with proper data in proper time. End action of transmission terminated signal L2_BUSY and reset internal status registers for transmitting action.