5. Detector supply and slow control system:
This is a first working diagram for the Si- readout system. PLEASE check it and see if you can find mistakes or inconsistency with your parts in there.
Status of preparation:Si readout for the engineering run
(HP, 4/28/99)
I briefly want to summaries the status of preparation for the engineering run concerning the silicon readout system
Two FECs will arrive tonight from latest engineering modifications at Argo to MIT together with 2 FEC Power supply boards
Last week we mainly worked on tests of the analog part of the FEC using a spectrometer module as "data" source. We found some distortions of analog readout signal (when probed on the ADC input) which was correlated to the clock pulses. The precise origin of this distortions is yet to be determined. This distortions "slow down" the analog signal, i.e. we need some additional time between switching the channel on with the clock pulse and digitizing it.
At present we consider to read the VA with a frequency of 1 MHz for the engineering run.
An additional adjustable delay has been implemented to optimize the timing between VA clock and ADC convert pulse.
Alan assembled all 13 octagon modules on the readout boards and we calibrated all three supermodules using the calibration station. The readout boards worked very nicely and gave consistent signal and noise results. One octagon module was found to be defect and needs to be replace for the enineering run.
We run a source test using the source test setup at MIT with the source on top and the scintilator below the detector. We measured a peak S/N of 12:1 which is perfectly consistent with both calibration data, noise measurements and calculated estimates (similar to the ones done for the spectrometer modules).
We connected one readout board to one FEC channel and read it using the standard FEC-DMU-MDC-Mercury chain (at a readout speed of 0.3MHz):
We compared the pedestal and noise measured on the FEC/DMU/MDC to the values measured at calibration and source test:
The intrinsic noise after common mode correction as perfectly identical to the source test data, which is very good news. The common mode noise as significantly larger in the FEC configuration than in the source test, we currently try to track it down.
The DMU and MDC needed for the engineering run are tested and work.
We hardware for the FFI was finished today and we started testing it now.
We ordered LV power supplies to feed the FECs for the engineering run. The voltages (4) need to be monitored. We plan to use a Keithley 2000-20 scanning multimeter , like the one for magnet and cooling system slow control, and order one. We received the detector bias voltage supply, it's tested and works.
Steve, what we need from the slow control GPIB system is
readout of the source voltage and current (1 value voltage, 1 value current)
5. Detector supply and slow control system:
This is a first working diagram for the Si- readout system. PLEASE check it and see if you can find mistakes or inconsistency with your parts in there.
6. List of components
In the following I tried to compile a list of components and equipment for the Si- readout in the engineering run. Please go through the list and let me know if there any thing that I forgot etc…
Component who status/ when comment 2 FEC MIT 30-Apr
will come to MIT tomorrow and need to be tested 2 FEC power boards MIT 30-Apr
will come to MIT tomorrow and need to be tested 1 FEC crate MIT ok 1 FEC crate fanunit MIT 4-May
1 FEC crate power connector MIT ? feeds supply voltages into the crate 6 C cables MIT 3-May
2 done by now 4 D cables MIT 3-May
2 done by now 6 L1/2 trigger cables MIT ok 160' ft coax cables with lemo connectors 1 DMU MIT ok 2 FFI MIT test started the hardware was finished and tests started today 8 cal boards MIT 5-May
tested in Austria, need to be shipped to MIT 2 Glink cables MIT ok 90Ohm thick Glink DMU to FEC 2 DMU-FEC flat cables MIT ok 10m 20 twisted pairs 3 eproms MIT 30-Apr
FEC startup eprom with final ro configuration for ER FEC +6V/5A power supply MIT ordered potential backup at MIT in case of late delivery FEC +3.3V/1A power supply MIT ordered deliv 5/6 potential backup at MIT in case of late delivery FEC -6V/1A power supply MIT ordered deliv 5/6 potential backup at MIT in case of late delivery FEC -3.3V/5A power supply MIT ordered potential backup at MIT in case of late delivery Keithley 2000-20 MIT ordered deliv 5/6 monitoring of FEC supply voltages GPIB monitoring for K2000-20 BNL ? 16 pair tw. FECMonitor cables MIT ok monitoring of FEC supply voltages (IR to ControlRoom) Vdet supply (0-200V) MIT ok detector supply Vdet GPIB control and readout BNL ? remote control and monitoring of detector voltage IsolationTransformer for FEC MIT ok UPS for FEC and DMU (2kW) MIT ok 1 MDC MIT ok 1 VME crate + fan for DMU/MDC MIT ok 2 fibres for readout MIT delivered need to be tested 2 AC power cords 150 ft each BNL clean power connection Control room to interaction region 1 ECL-TTL converter unit BNL converts ECL trigger signals to TTL trigger signals for DMU/MDC need min 4 ECL->TTLchannels
1 analog scope BNL 7-May
for testing various lemo cable/connectors terminator, banana plugs,etc
BNL 1 solder iron with fine tip BNL 7-May
for repairs 3 AC extension cords with 3-4 outlets each
BNL GPIB readout BNL 11-May
remote control and monitoring for slow control at IR-CtrlRoom 1 microscope MIT ok for module inspection 3 readout boards oct ANL/UIC ok will bring from MIT 13 Octagon ANL/UIC ok will come from MIT 1 replacement Octagon ANL/UIC 9-May
to replace one faulty Octagon out of the 13-gang 2 spare Octagon ANL/UIC 9-May
to test readout system at BNL while mounting octagons 2 Vertex Module ANL/UIC 9-May
octagon support structure ANL/UIC ok octagon mounting tools ANL/UIC octa/vertex light-tight enclosure ANL/UIC