Proposal for IDE Wafer probe tests to be performed on VAHDR1
The Phobos Collaboration
(contact: B. Wadsworth)
This note specifies the tests to be performed at IDE and test data to be recorded for VA-HDR1 chips. This summary is based on discussions of the test procedure with IDE held on October 7,1997 and November 18, 1997. Parameter values are based on IDE test results submitted to MIT on November 11,1997.
The purpose of the tests is first to determine that the chip is functional and second to measure parameters which indicate how the chip will perform in a large system, where many chips are controlled from the same bias lines. It is assumed that the tests are applied by an automated wafer probe setup in which the dies are held captive on the blue adhesive tape, so that a specific chip and its test data can be later correlated. The test steps and proposed acceptance criteria are described and a summary of the required output data per chip is given.
A. Outline of Tests:
1.) Current draw: 4 values
measure and record: Idd and Iss together with Vdd and Vss on the DUT board
with nominal operation parameters and bias currents:
Vdd | +2V ± 2% |
GND | 0V |
Vss | -2V ± 2% |
Vfp | -350mV ± 10mV |
Vfs | +760mV ± 10mV |
Ipreamp | 500mA ± 10mA |
Ishaper | 14mA ± 1mA |
Ibuffer | 140mA ± 3mA |
and quiescent operating conditions:
hold b | +2V |
clk b | +2V |
shift in b | +2V |
test on | -2V |
cal | 0V |
2.) Check operation of output shift register by detecting shift out signal: pass/fail
check for shift out b = +2V for clk pulses 1-127
= -2V for clk pulse 128
= +2V for clk pulse 129
3.) Measure voltage at bias current input pins Ipreamp, Isha, Ibuf: 3 values
4.) Record pedestal for each channel: 128 values
with zero calibration signal input
test_on = -2V
cal = 0V
5.) Measure channel-to-channel gain variation: 5*129 values
with supply voltages/currents specified under 1.)
hold_b signal delayed by 1.1 ms from positive edge of calibration signal
40fC ± 1% = > output S2
80fC ± 1% = > output S3
160fC ± 1% = > output S4
320fC ± 1% = > output S5
record average output amplitudes, i.e. average of amplitude for all good channels of one chip at a given input signal, AS1, AS2, AS3, AS4,AS5.
{mising formula} if j is a good channel and N the number of good channels
6.) Record channel number of sub-standard channels: max 2 values
Definition of "good" channel = output signals S1, S2, S3, S4, S5 are in a total 5% (± 2.5%) region around their average values AS1, AS2, AS3, AS4, AS5
Definition of "sub-standard" channel = output signals S1, S2, S3, S4, S5 are in a total 30% (±15%) region around their average values AS1, AS2, AS3, AS4, AS5
Definition of "dead" channel = output signals S1, S2, S3, S4, S5 are outside a 30% (±15%) region around their average values AS1, AS2, AS3, AS4, AS5 or the channel pedestal differs from the average pedestal by more than 50% of the dynamic range.
B. Outline of chip documentation
We intend to use this information in a database. For simplicity a plain text file would be preferred.
Preferred table format of the test record files: (they can be simple ASCII files)
File 1, Chip Table:
WAFER | CHIP | MEASURE-MENT | VALUE |
Wa# | Chip# | VDD | Value |
Wa# | Chip# | VSS | Value |
Wa# | Chip# | IDD | Value |
Wa# | Chip# | ISS | Value |
Wa# | Chip# | SOUT | 0 or 1 |
Wa# | Chip# | VPRE | Value |
Wa# | Chip# | VSHA | Value |
Wa# | Chip# | VBUF | Value |
Wa# | Chip# | SUBS | #SUBS |
Wa# | Chip# | DEAD | #DEAD |
Wa# | Chip# | AS1 | Value |
Wa# | Chip# | AS2 | Value |
Wa# | Chip# | AS3 | Value |
Wa# | Chip# | AS4 | Value |
Wa# | Chip# | AS5 | Value |
Data from other chips can follow in the same table |
WAFER is AMS wafer identification number
CHIP is the chip position number on the wafer
MEASUREMENT: is a character variable specifying the measurement type
VALUE is the measurement result. For SOUT please use 0 for FAIL and 1 for PASS. #SUBS and #DEAD are total number of Substandard and Dead channels on that chip.
The order of entries is not important, we will query this table based on (Wafer, Chip, Measurement) triplet
File 2, Channel Table
WAFER | CHIP | CHANNEL | INPUT TYPE | VALUE |
Wa# | Chip# | Chan# | 999 | Chan_quality |
Wa# | Chip# | Chan# | 0 | Value_ped |
Wa# | Chip# | Chan# | 20 | Value_s1 |
Wa# | Chip# | Chan# | 40 | Value_s2 |
Wa# | Chip# | Chan# | 80 | Value_s3 |
Wa# | Chip# | Chan# | 160 | Value_s4 |
Wa# | Chip# | Chan# | 320 | Value_s5 |
Wa# | Chip# | Chan# | 999 | Chan_quality |
Wa# | Chip# | Chan# | 0 | Value_ped |
Wa# | Chip# | Chan# | 20 | Value_s1 |
Wa# | Chip# | Chan# | 40 | Value_s2 |
Wa# | Chip# | Chan# | 80 | Value_s3 |
Wa# | Chip# | Chan# | 160 | Value_s4 |
Wa# | Chip# | Chan# | 320 | Value_s5 . |
Data from other chips can follow in the same table |
Order of entries is not important, we will query this table based on (Wafer, Chip, Channel) triplet.
INPUT TYPE is an integer measurement identification number with
"999": denotes the channel quality (test 6.)
"0": denotes channel pedestal (test 4.)
"20" to "320": denotes the input charge in the signal measurement (test 5.)
VALUE is the measurement result with
Chan_quality: 0=good channel, 1=substandard channel, 2=dead channel
Value_ped: channel pedestal
Value_sn: channel signal
C. Outline of acceptance criteria
This summarizes recent discussions concerning the chip acceptance based on tests performed at IDE.
C1.) chip calibration and shift_out functional
C2.) pedestal: channel to channel pedestal variation (peak-to-peak) less than 50fC equivalent input signal (i.e. 15MIPs); chip-to-chip average pedestal variation less than 70fC equivalent input signal (i.e. 20% of dynamic range)
C3.) average chip signals AS1 to AS5 are within ± 10% of the nominal signal (i.e. chip-to-chip gain variation <10%)
C4.) maximum