Global Feature Extractor – A Reconfigurable Computing Platform

BNL Reference Number: BSA 18-02

Patent Status: Provisional filed on October 4, 2018

TCP Technology
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A fully assembled third embodiment of the reconfigurable computer platform.

Reconfigurable computing systems use the field programmable gate array for fast processing. These computing platforms can route data and control data flow during processing, therefore they are primarily used for highly parallelized processing. The reconfigurable computing platform described can accept high data volume and run multiple algorithms in parallel on the same dataset. In the current system, 300 inputs and 100 outputs can bring data in and out of the computer platform. Such systems will be useful in pattern recognition, artificial intelligence and neural networks.


This computing platform is implemented using the industry advanced telecommunications computing architecture (ATCA) format. The computing platform has four novel concepts implemented in the system: 1) Distribution of power to the FPGAs is implemented by generation of the voltages required as close as possible to each processor FPGA from a common higher voltage distributed at the periphery of the printed circuit board. This method differs from the commonly used single point voltage generation that leads to loss of power by Ohmic resistance in the printed circuit lines. 2) The interconnection between FPGA lines require the use of a capacitor to decouple the DC voltage. Given the lack of space on the high-density board, the capacitor was placed on the back side of a multilayer printed circuit board. 3) Data transfer, synchronism of data processing, and output are all controlled by a central clock. On this board the board clock is synchronized to an external clock that allows synchronous board to board operations.


The computing platform can receive low resolution data on approximately 300 optical fibers at a rate of 300 Tera bits per second (Tb/s) outputting the results of calculation on approximately 100 optical fibers at a rate of 100 Tera bits per second. The architecture of the platform is such that optical signals are converted to electrical signals as physically near as possible to the corresponding FPGA to substantially eliminate signal distortion, reflection, and cross-talk in high-speed electrical signals. In addition, each of the FPGAs is interconnected via high-speed links. These features enable synchronous operation of each of the FPGA-based processors in the platform.

Applications and Industries

This system can be used in pattern recognition and correlation analysis, including energy grid monitoring and homeland security; cryptography, including data encryption and decryption; and artificial intelligence, including neural networks, natural language processing, and deep learning.

Journal Publication
  • The implementation of Global Feature EXtractor (gFEX) - the ATLAS Calorimeter Level 1 Trigger system for LHC Run-3 upgrade
Mailing Address

Office of Technology Commercialization and Partnerships
Brookhaven National Laboratory
Building 490C
P.O. Box 5000
Upton, New York 11973-5000

Have Questions?

For more information about this technology, contact Poornima Upadhya, (631) 344-4711,

Category: electronics & instrumentation

Tags: electronics, homeland security