Thursday, May 25, 2017, 2:30 pm — Large Conference Room, Bldg. 535
Analog-to-digital converters (ADCs) play a crucial role in the interface between physical signals found in Nature (analog domain) and abstract bits used in digital systems (digital domain). In this seminar, firstly, after a short introduction to ADC basics, a first-order incremental delta-sigma ADC with 10-bit, ~ 100 S/s, and 11 µW designed in a 0.6 µm CMOS technology will be presented. This ADC architecture is suitable for DC-like measurements, and despite its noise shaping nature, it preserves a one-to-one mapping between the sampled analog input and the digital output. We will then move to a two-channel time-interleaved pipeline ADC with 8-bit, 120 MS/s, 14 mW, and 530x230 µm^2 fabricated in a 130 nm CMOS technology. This ADC architecture is based on a very interesting principle known in the literature as "MOS parametric amplification," and is suitable for high speed data conversion, e.g. in communication, IF sampling, etc. Following these two past personal developments, the present state-of-the-art summary on ADCs will be presented, emphasizing the recent trend toward hybrid ADCs, which blends different architectures into one ADC design enabling new breakthroughs in accuracy, speed, power efficiency, and area, particularly in advanced (< 65 nm) technology nodes.
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