Center for Functional Nanomaterials Seminar

Data communications has the potential to deliver the necessary information bandwidth, latency, and power consumption required for new generations of VLSI [1]. However, requirements dictated by practical optoelectronic integration not only necessitates the miniaturization of optical devices towards truly nano-scale, but also mandates material compatibility and nonintrusive integration with CMOS technology, which are often overlooked in the effort to optimize device performance. Optical detection is a quintessential function within transceivers for data communications. Current guided-wave photodetector designs, utilizing germanium [1], 2-D materials [2], resonant cavities [3], or plasmonic effects [4], cannot fulfill all these requirements simultaneously. Moreover, their junctions, where photogeneration takes place, are typically implemented by utilizing crystalline materials, which are inherently incompatible with CMOS back-end processing and will likely dictate significant modifications to front-end-of-line CMOS processes. Here we report a novel architecture for on-chip integrated hybrid plasmonic devices that can meet the aforementioned criteria for the first time. In this work, we demonstrate experimentally a highly sensitive guided-wave detector that is wavelength-scale in 3 dimensions, non-resonant with a single active junction that is fully implemented with CMOS-compatible amorphous materials on SOI. It is shown experimentally that within a 5μm-long hybrid plasmonic waveguide, we can obtain a dark current of 0.2nA at 7V leading to a minimum detectable optical power, or minimum sensitivity, of -35dBm and static power consumption of 1.2nW. The devices were also tested to be operational within a wide temperature range of 15-100°C and optical wavelength range of 1.2- 1.8μm. The reduction in footprint and active junction areas also lead to a parasitic capacitance of only 8fF, enabling an RC frequency cut-off of 400GHz. Moreover, the hybrid plasmonic waveguide can be integrated to silicon photonics with only 1.5dB coupling loss, demonstrating the potential for integration of amorphous-based plasmonic devices with conventional dielectric based optical interconnects and electronics using back-end processing. This hybrid plasmonic architecture consists of an asymmetric hybrid plasmonic waveguide (AHPW), a multilayer stack built from Si-SiO2-Al-αSi layers as shown in Fig. 1. When the 10nm-thick Al layer is sufficiently thin, the hybrid plasmonic waveguide (HPW) mode supported by the Si-SiO2-Al layers and the surface plasmon polariton (SPP) mode supported by the Al-αSi interface become coupled and results in the formation of antisymmetric and symmetric supermodes. The optical mode exhibits nanoscale power confinement in the layers adjacent to the metal, offering high light-matter interaction for enhanced performance in active optoelectronic components. In our work, we focus on the utilization of the symmetric super-mode as the signal carrier because of its highly tunable absorption characteristics [5]. The absorption per length can increase up to two orders of magnitude by simply varying the core width, allowing the implementation of plasmonic devices that can take advantage of this flexibility under the same vertical structure and fabrication steps. The small momentum and field mismatch of the symmetric supermode also allows these structures to be integrated to conventional dielectric waveguides with high coupling efficiency. The mode evolution starts from an input signal excited from the TM-mode of an 800nm-wide silicon nanowire into the 200nm-wide AHPW which is then tapered up to 620nm for maximized absorption. Via this non-resonant direct end-butt coupling scheme, we can achieve 1.5dB coupling loss, allowing efficient integration of long-range dielectric signal carriers with sub-micron scale plasmonics within minimal device footprints.