Wednesday, June 20, 2012, 2:30 pm — Large Conference Room, Bldg. 535
Very fast readout, large area CCD sensors were designed and fabricated by e2V Technologies, using full column-parallel architecture and bump-bonded ASIC readout on 20 µm pitch in a hybrid assembly. Two generations of prototype CCDs were successfully tested by a collaboration of UK universities and Rutherford Appleton Laboratory. The emphasis was placed on fast readout, at 20ns per row, while keeping the clock amplitude low to reduce power dissipation. A range of prototype small scale CCDs were also designed to study the limits of operation at low clock amplitudes.
An alternative approach to the fast readout challenge was developed in the form of an In-situ Storage Image Sensor (ISIS) by the same team. One small device was manufactured by e2V using conventional CCD process. A device based on the same principles but using 0.18µm CMOS process was designed and manufactured as well, pioneering CCD-style multiple charge transfer in a custom buried channel. Additionally, for future developments requiring large pixels like the Silicon Pixel Tracker, some ideas for CMOS pixels with charge transfer are presented.
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