Assistant Computational Scientist, Comp. for Nat'l Sec, Computational Science Init
Brookhaven National Laboratory
Computational Science Init
P.O. Box 5000
Upton, NY 11973-5000
I am currently an assistant scientist in the Computational Science Initiative of Brookhaven National Laboratory. I am generally interested in computer architecture and programming model. My current research focuses on memory system optimization, with an emphasis on architecture simulation, programming models, and compiler. My CV can be found here.
Before joining BNL, I worked at the Department of Computer Science of Rutgers University as a postdoc to carry out GPGPU research between Sept. 2014 and Aug. 2016, I obtained my PhD degree in computer architecture from the Microprocessor Research and Development Center, Peking University in 2014.
- Li L, Chapman B (2019) Compiler assisted hybrid implicit and explicit GPU memory management under unified address space. Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis. doi: 10.1145/3295500.3356141
- Li L, Finkel H, Kong M, Chapman B (2018) Manage OpenMP GPU Data Environment Under Unified Address Space. Lecture Notes in Computer Science 69–81. doi: 10.1007/978-3-319-98521-3_5
- Li L, Geda R, Hayes AB, Chen Y, Chaudhari P, Zhang EZ, Szegedy M (2017) A Simple Yet Effective Balanced Edge Partition Model for Parallel Computing. Proceedings of the ACM on Measurement and Analysis of Computing Systems 1:1–21. doi: 10.1145/3084451
- Mishra A, Li L, Kong M, Finkel H, Chapman B (2017) Benchmarking and Evaluating Unified Memory for OpenMP GPU Offloading. Proceedings of the Fourth Workshop on the LLVM Compiler Infrastructure in HPC - LLVM-HPC'17. doi: 10.1145/3148173.3148184
- Li L, Hayes AB, Song SL, Zhang EZ (2016) Tag-Split Cache for Efficient GPGPU Cache Utilization. Proceedings of the 2016 International Conference on Supercomputing. doi: 10.1145/2925426.2926253
- Hayes AB, Li L, Chavarría-Miranda D, Song SL, Zhang EZ (2016) Orion. Proceedings of the 17th International Middleware Conference. doi: 10.1145/2988336.2988355
- Li L, Lu J, Cheng X (2014) Block value based insertion policy for high performance last-level caches. Proceedings of the 28th ACM international conference on Supercomputing - ICS '14. doi: 10.1145/2597652.2597653
- Li L, Tong D, Xie Z, Lu J, Cheng X (2012) Improving inclusive cache performance with two-level eviction priority. 2012 IEEE 30th International Conference on Computer Design (ICCD). doi: 10.1109/iccd.2012.6378668
- Li L, Tong D, Xie Z, Lu J, Cheng X (2012) Optimal bypass monitor for high performance last-level caches. Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12. doi: 10.1145/2370816.2370862